As differential amplifiers used as amplifiers in electronic equipment and semiconductor integrated circuits, there are conventional ones disclosed in Document 1 (“Semiconductor Circuit Design Technology,” compiled under the supervision of Tokumichi Tamai, Nikkei B P, Inco., First Edition, Page 308) and Document 2 (“Analysis and Design of Analog Integrated Circuits,” Paul R. Gray and Robert G Meyer, John Wiley & Sons, Inc., Third Edition, Page 244).
FIG. 29 shows a circuit diagram of a conventional differential amplifier as disclosed in Document 1 or 2. In the drawing, 1 and 2 are first and second input terminals to which a differential signal is inputted, M1 and M2 are n-channel MOS transistors for composing a differential couple and receiving the signals inputted to the first and second input terminals, M3 is an n-channel MOS transistor for composing a tail current source for the differential amplifier, NGB is a gate voltage application terminal for operating the n-channel MOS transistor as a current source, VSS is a negative power source for the circuit or a terminal to which the ground is applied, and 16 and 17 are output terminals for outputting signals converted to currents by the differential couple M1 and M2.
A description will be given to a differential amplifier thus constructed. A current in the n-channel MOS transistor M3 is distributed between the two n-channel MOS transistors M1 and M2 depending on a voltage difference between two signals composing the differential signal inputted to the first and second input terminals 1 and 2. When the two signals composing the differential signal have equal input voltages, a current conversion rate is defined as a conductance gm and, if the conductance gm of each of the n-channel MOS transistors composing the differential couple is assumed to be gmn, the gmn is expressed asgmn=Ids/(Vgs−Vthn)where Ids is a current flowing in the MOS transistor, Vgs is a gate-source voltage, and Vthn is the threshold voltage of the n-channel MOS transistor.
When the respective voltages of the input signals are low, however, a flowing current is reduced disadvantageously because the n-ch MOS transistor M3 operates in a non-linear region so that an intrinsic operation is not obtainable. Thus, the conventional circuit of FIG. 29 has a drawback that the range of the input operating voltage is limited to a voltage range within which the n-channel MOS transistor M3 composing the tail current source operates in a saturation region.
FIG. 30 shows a differential amplifier which implements the same function as the conventional circuit of FIG. 29 by using p-channel MOS transistors. In the drawing, 1 and 2 are input terminals, M22 and M23 are p-channel MOS transistors composing a differential couple, M24 is a p-channel MOS transistor composing a tail current source for the differential amplifier, PGB is a gate voltage application terminal for operating the p-channel MOS transistor as the current source, VDD is a terminal to which a positive power source for the circuit is applied, and 34 and 35 are output terminals for outputting the signals converted to currents.
In the differential amplifier thus constructed also, the current conversion rate is obtained as the conductance gm in the same manner as in the circuit composed of the n-channel MOS transistors. Accordingly, if the conductance gm of each of the p-channel MOS transistors is assumed to be gmp, the gmp is expressed asgmp=Ids/(Vsg−Vthp)where Ids is a current flowing in the MOS transistor, Vsg is a source-gate voltage, and Vthp is the threshold voltage of the p-channel MOS transistor.
If the input voltages to the differential amplifier shown in FIG. 30 are high, however, the p-channel MOS transistor M24 operates in a linear region so that a current flowing therein is reduced disadvantageously and an intrinsic operation is not obtainable. Accordingly, the differential amplifier of FIG. 30 also has a drawback that the range of the input operating voltage is limited to a voltage range within which the p-channel MOS transistor M24 composing the tail current source operates in the saturation region.
Thus, each of the differential amplifiers shown in FIGS. 29 and 30 has the problem that the range of the input operating voltage is limited.
As an amplifier which operates in the entire range of the input operating voltage and thereby solves such a problem, there is a conventional one disclosed in Document 3 (Domestic-Phase PCT Patent Application No. HEI 11-500883).
FIG. 31 is a circuit diagram of a differential amplifier as a part of the amplifier disclosed in Patent Document 3 mentioned above. In FIG. 31, M6 and M7 are n-channel MOS transistors composing a differential couple, M27 and M28 are p-channel MOS transistors composing a differential couple, 67, 32, and 36 are tail current sources for composing respective differential amplifiers, 27 and 38 are current sources for canceling out currents from the tail current sources for the differential amplifiers, M25 and M26 are n-channel MOS transistors for sensing the respective operating states of the tail current sources 6 and 7 and causing the ON/OFF operation of the current source 38, and M29 and M30 are p-channel MOS transistors for sensing the respective operating states of the tail current sources 32 and 36 and causing the ON/OFF operation of the current source 27.
FIG. 32 is a block diagram for illustrating the operation of the amplifier of Document 3 mentioned above. In the drawing, 4 is a differential couple composed of n-channel MOS transistors M1 and M2, 5 is a differential couple composed of the n-channel MOS transistors M6 and M7, 30 is a differential couple composed of the p-channel MOS transistors M27 and M28, 31 is a differential couple composed of p-channel MOS transistors M22 and M23, 28 is a switch composed of the p-channel MOS transistors M29 and M30, 29 is a switch generated by the operation of the n-channel MOS transistors M6 and M7, 37 is a switch composed of the n-channel MOS transistors M25 and M26, 33 is a switch generated by the operation of the p-channel MOS transistors M22 and M23, 10 is a current synthesis and amplification circuit for synthesizing and amplifying currents outputted from the output terminals of the differential amplifiers.
A description will be given to the operation of the differential amplifiers thus constructed. In the amplifier of Document 3, the problem of each of the conventional circuits already described with reference to FIGS. 29 and 28, which is the limited operation range of the input voltage to the differential amplifier, has been solved by operating the differential couple of the n-channel MOS transistors and the differential couple of the p-channel MOS transistors in combination. Specifically, in the amplifier of Document 3, the differential couples 30 and 31 operate at a voltage in the vicinity of that of the negative power source VSS for the circuit, the differential couples 5 and 30 operate at an intermediate voltage, and the differential couples 4 and 5 operate at a high voltage in the vicinity of that of the positive power source VDD for the circuit. Accordingly, there are three expressions for the conversion rate gm of the differential amplifier in correspondence with the three cases. In the vicinity of the ground potential VSS, the conversion rate is expressed asgm=2·gmp.
At the intermediate voltage, the conversion rate is expressed asgm=gmn+gmp.
In the vicinity of the power source voltage VDD, the conversion rate is expressed asgm=2·gmn.
Thus, the differential amplifier composing the amplifier of Document 3 mentioned above is operable in the entire range of the input voltage but is required to satisfy a relationship represented bygmn=gmpsuch that the conversion rate gm of each of the differential amplifiers is held constant. However, the relationship cannot necessarily be satisfied if variations in a diffusion process are taken into consideration. Thus, the differential amplifiers composing the amplifier of Document 3 have the drawback that, to hold the conversion rate constant over the entire range of the input voltage, the necessity to equate the characteristics of the n-channel MOS transistors with those of the p-channel MOS transistors, though the differential amplifiers composing the amplifier of Document 3 are operable over the entire range of the input voltage. In addition, the output mode of the differential amplifier of Document 3 is an output voltage in the vicinity of the VDD with the differential couple composed of n-channel MOS transistors, while it is an operating voltage in the vicinity of the VSS with the differential couple composed of p-channel MOS transistors, so that currents having different operating voltage points should be synthesized and the synthesis of the currents becomes complicated.
As the amplifier operating over the entire range of the input operating voltage, there is also a conventional one disclosed in Document 4 (Japanese Laid-Open Patent Publication No. HEI 8-18355).
FIG. 33 shows a circuit diagram of a differential amplifier which is a part of the operational amplifier disclosed in Document 4. In FIG. 33, M5 and M10 are p-channel MOS transistors for level-shifting input signals, M1 and M2 are n-channel MOS transistors composing a differential couple, M6 and M7 are n-channel MOS transistors composing another differential couple, 6 and 7 are tail current sources for composing differential amplifiers, and 39 and 40 are current sources for driving the p-channel MOS transistors.
FIG. 34 is a block diagram for illustrating the operation of the operational amplifier of Document 4 which is shown specifically in FIG. 33. In the drawing, 8 and 9 are level shift circuits for shifting the voltages levels of differential signal, 4 and 5 are a differential couple composed of n-channel MOS transistors, 10 is a circuit for synthesizing and amplifying currents outputted from the output terminals of the differential amplifier, and 3 is an output of the operational amplifier.
A description will be given to the operation of the differential amplifier of Document 4 thus constructed. In the operational amplifier of Document 4, the differential couple composed of the n-channel MOS transistors and the level shift circuits are combined to operate, whereby the conventional problem illustrated with reference to FIG. 29, which is the limited range of the input operating voltage of the differential amplifier, is solved. That is, in the operational amplifier of Document 4, the differential couple 5 operates at a voltage in the vicinity of the negative power source VSS for the circuit, the differential couples 4 and 5 operate at an intermediate voltage, and the differential couple 4 operates at a high voltage in the vicinity of the positive power source VDD for the circuit. Thus, there are three expressions for the conversion rate gm of the differential amplifier in correspondence with the three cases. In the vicinity of the ground potential VSS, the conversion rate is expressed asgm=gmn.
At the intermediate voltage, the conversion rate is expressed asgm=2·gmn.
In the vicinity of the power source voltage VDD, the conversion rate is expressed asgm=gmn.Therefore, the differential amplifier composing the operational amplifier of Document 4 mentioned above is operable over the entire range of the input voltage but, even if the respective conversion rates of the differential couples 4 and 5 are changed, the conversion rate of the differential amplifier cannot be held constant. Accordingly, the differential amplifier composing the operational amplifier of Document 4 has the drawback that the conversion rate cannot be held constant over the entire range of the input voltage.
Against this backdrop, a conventional differential amplifier capable of operating over the entire range of the input voltage and also holding constant the conversion rate over the entire range of the input voltage is disclosed in Document 5 (Japanese Laid-Open Patent Publication No. HEI 8-18354).
FIG. 35 shows a circuit diagram of the differential amplifier composing an operational amplifier of FIG. 5. In the drawing, M31, M33, M35, M36, and M37 are a differential amplifier and a diode load each for measuring a current variation resulting from the voltage level of the differential signal, M32, M34, M38, and M39 are p-channel MOS transistors composing a current subtract circuit, and M40 and M41 are n-channel MOS transistors composing the current subtract circuit. The other circuit structure is the same as in FIG. 33.
FIG. 36 shows a block diagram for illustrating the operation of the operational amplifier of Document 5. In the drawing, 41 is a current measure circuit for measuring a current variation resulting from the voltage level of the differential signal, 42 is a current subtract circuit for subtracting a current sensed by the current measure circuit 41 from an intrinsic current, and M8 is a tail current source controlled by an output of the current subtract circuit 42.
A description will be given to the operation of the differential amplifier of Document 5 thus constructed. In the operational amplifier of Document 5, the differential couple composed of the n-channel MOS transistors and the level shift circuit are combined to operate, whereby the foregoing conventional problem described with reference to FIG. 29, which is the limited range of the input operating voltage of the differential amplifier, is solved. That is, in the operational amplifier of Document 5, the differential couple 5 operates at a voltage in the vicinity of a negative power source VSS for the circuit, only the current differential couple 4 operates at an intermediate voltage by stopping the current in the n-channel MOS transistor M8 by using the current sense circuit 41 and the current subtract circuit 42, and the differential couple 4 operates even at a high voltage in the vicinity of the positive power source VDD for the circuit. Thus, there are two expressions for the conversion rate gm of the differential amplifier in correspondence with the two cases. In the vicinity of the ground potential VSS, the conversion rate is expressed asgm=gmn.
At the intermediate voltage and in the vicinity of the power source potential VDD, the conversion rate is expressed asgm=gmn.
Hence, the differential amplifier composing the operational amplifier of Document 5 is capable of operating over the entire range of the input voltage and the conversion rate thereof can be held constant.
Problem to be Solved
However, the differential amplifier of Document 5 has the drawback that it cannot respond quickly to high-speed and large-amplitude input signals. This is because current mirror circuits ((M31 and M32), (M38 and M39)) are used for the current measure circuit 41 and the current subtract circuit 42. The current mirror circuit has the drawback that charge accumulated in the gate capacitance of each of the MOS transistors cannot be extracted swiftly during the ON-to-OFF operation thereof and the operating speed is lowered, though an expected operating speed is guaranteed for the current mirror circuit during the OFF-to-ON operation thereof. Thus, the differential amplifier composing the operational amplifier of Document 5 has the drawback that it cannot operate at a high speed.